IJERGS · Volume 2, Issue 5 · September-October 2014 Edition
DESIGN OF 16-BIT DATA PROCESSOR USING FINITE STATE MACHINE IN VERILOG
| Journal | International Journal of Engineering Research and General Science (IJERGS) |
|---|---|
| ISSN | 2091-2730 |
| Volume | 2 |
| Issue | 5 |
| Edition | September-October 2014 Edition |
| Year | 2014 |
| Pages | page 142-148 |
| Publisher | P&R Publication |
How to cite
Shashank Kaithwas, Pramod Kumar Jain (2014). DESIGN OF 16-BIT DATA PROCESSOR USING FINITE STATE MACHINE IN VERILOG. International Journal of Engineering Research and General Science, 2(5), 142-148. ISSN 2091-2730. https://www.ijergs.org/article/v2-i5-20.html