IJERGS · Volume 2, Issue 6 · November-December 2014 Edition
DESIGN AND IMPLEMENTATION OF AN ON-CHIP TIMING BASED PERMUTATION NETWORK FOR MULTIPROCESSOR SYSTEM ON CHIP
| Journal | International Journal of Engineering Research and General Science (IJERGS) |
|---|---|
| ISSN | 2091-2730 |
| Volume | 2 |
| Issue | 6 |
| Edition | November-December 2014 Edition |
| Year | 2014 |
| Pages | page 762-766 |
| Publisher | P&R Publication |
How to cite
Ms Lavanya Thunuguntla, Saritha Sapa (2014). DESIGN AND IMPLEMENTATION OF AN ON-CHIP TIMING BASED PERMUTATION NETWORK FOR MULTIPROCESSOR SYSTEM ON CHIP. International Journal of Engineering Research and General Science, 2(6), 762-766. ISSN 2091-2730. https://www.ijergs.org/article/v2-i6-96.html